BURAQ: A Re-Configurable Processor Toolkit for VLlW Architectures

Re-configurable application specific DSP architectures are becoming the heart of modern communication and signal processing applications. These architectures are optimized for a set of applications, and different applications may require different processors. This increasing demand for application specific DSPs emphasize efficient methodological framework for design cycle of a new DSP and accompanying tools (assembler, linker, simulator/debugger, hardware generator). This paper introduces a novel toolkit, BURAQ, that optimizes cost, efficiency and turn around time of a VLIW DSPs. BURAQ accepts an Instruction and Architecture Description (IAD) file that represents the DSP and its instruction set at a higher level of abstraction, in a proprietary language. With data model, functional unit model and instruction set model, it generates the above-mentioned tools for the processor. In order to prove the quality of the tools, we model two of the most widely used VLIWs i.e. TI’s TMS320C6x and StarCore’s SC140 in BURAQ.